On-chip ESD detection circuit for system-level ESD protection design

Ming-Dou Ker*, Wan Yen Lin, Cheng Cheng Yen, Che Ming Yang, Tung Yang Chen, Shih Fan Chen

*此作品的通信作者

    研究成果: Conference contribution同行評審

    9 引文 斯高帕斯(Scopus)

    摘要

    A new on-chip CR-based electrostatic discharge (ESD) detection circuit for system-level ESD protection design is proposed in this work. The circuit performance to detect positive or negative electrical transients generated by system-level ESD tests has been analyzed in HSPICE simulation and verified in silicon chip. The experimental results in a 0.13-μm CMOS process have confirmed that the proposed detection circuit can detect ESD-induced transient disturbance during system-level ESD zapping. The detection results can be used as system recovery firmware index to improve the immunity of CMOS IC products against system-level ESD stress.

    原文English
    主出版物標題ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings
    頁面1584-1587
    頁數4
    DOIs
    出版狀態Published - 1 12月 2010
    事件2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology - Shanghai, 中國
    持續時間: 1 11月 20104 11月 2010

    出版系列

    名字ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings

    Conference

    Conference2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology
    國家/地區中國
    城市Shanghai
    期間1/11/104/11/10

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