TY - JOUR
T1 - On-Chip Capacitance Measurement Circuits in VSLI Structures
AU - Iwai, Hiroshi
AU - Kohyama, Susumu
PY - 1982/10
Y1 - 1982/10
N2 - A precise capacitance measurement technique is described. This technique is based on a principle of capacitively divided ac voltage measurement. Details of the measurement procedure and test pattern configuration is also discussed. Utilizing the technique, precise capacitance measurements were carried out, which were practically difficult with direct measurements, and size effects of the small geometry capacitances were measured and evaluated. The technique was found to be practical and accurate, and besides, the test device can be integrated on an LSI chip, thus it appears to be very effective in VLSI development.
AB - A precise capacitance measurement technique is described. This technique is based on a principle of capacitively divided ac voltage measurement. Details of the measurement procedure and test pattern configuration is also discussed. Utilizing the technique, precise capacitance measurements were carried out, which were practically difficult with direct measurements, and size effects of the small geometry capacitances were measured and evaluated. The technique was found to be practical and accurate, and besides, the test device can be integrated on an LSI chip, thus it appears to be very effective in VLSI development.
UR - http://www.scopus.com/inward/record.url?scp=0020193819&partnerID=8YFLogxK
U2 - 10.1109/T-ED.1982.20924
DO - 10.1109/T-ED.1982.20924
M3 - Article
AN - SCOPUS:0020193819
VL - 29
SP - 1622
EP - 1626
JO - Ieee Transactions On Electron Devices
JF - Ieee Transactions On Electron Devices
SN - 0018-9383
IS - 10
ER -