On-Chip Capacitance Measurement Circuits in VSLI Structures

Hiroshi Iwai, Susumu Kohyama

研究成果: Article同行評審

15 引文 斯高帕斯(Scopus)

摘要

A precise capacitance measurement technique is described. This technique is based on a principle of capacitively divided ac voltage measurement. Details of the measurement procedure and test pattern configuration is also discussed. Utilizing the technique, precise capacitance measurements were carried out, which were practically difficult with direct measurements, and size effects of the small geometry capacitances were measured and evaluated. The technique was found to be practical and accurate, and besides, the test device can be integrated on an LSI chip, thus it appears to be very effective in VLSI development.

原文English
頁(從 - 到)1622-1626
頁數5
期刊IEEE Transactions on Electron Devices
29
發行號10
DOIs
出版狀態Published - 10月 1982

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