TY - JOUR
T1 - On board processor development for NASA's spacebone imaging radar with VLSI system-on-chip technology
AU - Fang, Wai-Chi
AU - Jin, Michael Y.
PY - 2004
Y1 - 2004
N2 - This paper reports a preliminary study result of an on-board spaceborne SAR processor. It consists of a processing requirement analysis, functional specifications, and implementation with VLSI system-on-chip technology. Finally, a minimum version of this VLSI on-board processor designed for performance evaluation and for partial demonstration is illustrated.
AB - This paper reports a preliminary study result of an on-board spaceborne SAR processor. It consists of a processing requirement analysis, functional specifications, and implementation with VLSI system-on-chip technology. Finally, a minimum version of this VLSI on-board processor designed for performance evaluation and for partial demonstration is illustrated.
UR - http://www.scopus.com/inward/record.url?scp=4344718551&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2004.1329418
DO - 10.1109/ISCAS.2004.1329418
M3 - Conference article
AN - SCOPUS:4344718551
SN - 0271-4310
VL - 2
SP - II901-II904
JO - Proceedings - IEEE International Symposium on Circuits and Systems
JF - Proceedings - IEEE International Symposium on Circuits and Systems
T2 - 2004 IEEE International Symposium on Cirquits and Systems - Proceedings
Y2 - 23 May 2004 through 26 May 2004
ER -