On-board fault-tolerant SAR processor for spaceborne imaging radar systems

Wai-Chi  Fang*, Charles Le, Stephanie Taft

*此作品的通信作者

研究成果: Conference article同行評審

10 引文 斯高帕斯(Scopus)

摘要

A real-time high-performance and fault-tolerant FPGA-based hardware architecture for the processing of synthetic aperture radar (SAR) images has been developed for advanced spaceborne radar imaging systems. In this paper, we present the integrated design approach, from top-level algorithm specifications, system architectures, design methodology, functional verification, performance validation, down to hardware design and implementation.

原文English
文章編號1464614
頁(從 - 到)420-423
頁數4
期刊Proceedings - IEEE International Symposium on Circuits and Systems
DOIs
出版狀態Published - 1 十二月 2005
事件IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan
持續時間: 23 五月 200526 五月 2005

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