TY - JOUR
T1 - On-board fault-tolerant SAR processor for spaceborne imaging radar systems
AU - Fang, Wai-Chi
AU - Le, Charles
AU - Taft, Stephanie
PY - 2005/12/1
Y1 - 2005/12/1
N2 - A real-time high-performance and fault-tolerant FPGA-based hardware architecture for the processing of synthetic aperture radar (SAR) images has been developed for advanced spaceborne radar imaging systems. In this paper, we present the integrated design approach, from top-level algorithm specifications, system architectures, design methodology, functional verification, performance validation, down to hardware design and implementation.
AB - A real-time high-performance and fault-tolerant FPGA-based hardware architecture for the processing of synthetic aperture radar (SAR) images has been developed for advanced spaceborne radar imaging systems. In this paper, we present the integrated design approach, from top-level algorithm specifications, system architectures, design methodology, functional verification, performance validation, down to hardware design and implementation.
UR - http://www.scopus.com/inward/record.url?scp=34047255049&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2005.1464614
DO - 10.1109/ISCAS.2005.1464614
M3 - Conference article
AN - SCOPUS:34047255049
SN - 0271-4310
SP - 420
EP - 423
JO - Proceedings - IEEE International Symposium on Circuits and Systems
JF - Proceedings - IEEE International Symposium on Circuits and Systems
M1 - 1464614
T2 - IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005
Y2 - 23 May 2005 through 26 May 2005
ER -