Novel Sub-10-nm Gate-all-around Si nanowire channel Poly-Si TFTs with raised source/drain

Yi Hsien Lu*, Po Yi Kuo, Yi Hong Wu, Yi Hsuan Chen, Tien-Sheng Chao

*此作品的通信作者

研究成果: Article同行評審

20 引文 斯高帕斯(Scopus)

摘要

We have successfully fabricated novel sub-10-nm gate-all-around Si nanowire (NW) poly-Si TFTs with raised source/drain structure (GAA RSDNW-TFTs). The Si NW dimension is about 7 time12 nm. A superior smooth elliptical shape is obtained, for the first time, in the category of poly-Si NW TFTs through the use of a novel fabrication process requiring no advanced lithographic tools. The GAA RSDNW-TFTs exhibit low supply gate voltage (3 V), steep subthreshold swing sim 99 mV/dec, and high IOI OFF 107(VD) = V-1)without hydrogen-related plasma treatments. Furthermore, the DIBL of GAA RSDNW-TFTs is well controlled. These improvements can be attributed to the 3-D gate controllability, raised S/D structure, and sub-10-nm Si NW channel. These novel GAA RSDNW-TFTs are, thus, quite suitable for system-on-panel and 3-D IC applications.

原文English
文章編號5671463
頁(從 - 到)173-175
頁數3
期刊IEEE Electron Device Letters
32
發行號2
DOIs
出版狀態Published - 1 2月 2011

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