Novel input ESD protection circuit with substrate-triggering technique in a 0.25-μm shallow-trench-isolation CMOS technology

Ming-Dou Ker; Tung Yang Chen; Chung-Yu Wu; Howard Tang; Kuan Cheng Su; S. W. Sun

doi:10.1109/ISCAS.1998.706879

Novel input ESD protection circuit with substrate-triggering technique in a 0.25-μm shallow-trench-isolation CMOS technology

Ming-Dou Ker^*, Tung Yang Chen, Chung-Yu Wu, Howard Tang, Kuan Cheng Su, S. W. Sun

^*此作品的通信作者

電子研究所

研究成果: Conference article › 同行評審

30 引文斯高帕斯（Scopus）

摘要

A substrate-triggering technique, to increase the ESD robustness and to reduce the trigger voltage of the ESD protection device, is proposed to improve the ESD-protection efficiency of the input ESD protection circuit in deep-submicron CMOS technology. Through suitable substrate-triggering design on the device structure, this proposed input ESD protection circuit can successfully protect the thinner gate oxide (50 angstroms) of the input stage in a 0.25-μm CMOS technology and sustain an ESD level above 2000 V without extra process modification.

原文	English
頁（從 - 到）	212-215
頁數	4
期刊	Proceedings - IEEE International Symposium on Circuits and Systems
卷	2
DOIs	https://doi.org/10.1109/ISCAS.1998.706879
出版狀態	Published - 1998
事件	Proceedings of the 1998 IEEE International Symposium on Circuits and Systems, ISCAS. Part 5 (of 6) - Monterey, CA, USA 持續時間: 31 5月 1998 → 3 6月 1998

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10.1109/ISCAS.1998.706879

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abstract = "A substrate-triggering technique, to increase the ESD robustness and to reduce the trigger voltage of the ESD protection device, is proposed to improve the ESD-protection efficiency of the input ESD protection circuit in deep-submicron CMOS technology. Through suitable substrate-triggering design on the device structure, this proposed input ESD protection circuit can successfully protect the thinner gate oxide (50 angstroms) of the input stage in a 0.25-μm CMOS technology and sustain an ESD level above 2000 V without extra process modification.",

author = "Ming-Dou Ker and Chen, {Tung Yang} and Chung-Yu Wu and Howard Tang and Su, {Kuan Cheng} and Sun, {S. W.}",

year = "1998",

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journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

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T1 - Novel input ESD protection circuit with substrate-triggering technique in a 0.25-μm shallow-trench-isolation CMOS technology

AU - Ker, Ming-Dou

AU - Chen, Tung Yang

AU - Wu, Chung-Yu

AU - Tang, Howard

AU - Su, Kuan Cheng

AU - Sun, S. W.

PY - 1998

Y1 - 1998

N2 - A substrate-triggering technique, to increase the ESD robustness and to reduce the trigger voltage of the ESD protection device, is proposed to improve the ESD-protection efficiency of the input ESD protection circuit in deep-submicron CMOS technology. Through suitable substrate-triggering design on the device structure, this proposed input ESD protection circuit can successfully protect the thinner gate oxide (50 angstroms) of the input stage in a 0.25-μm CMOS technology and sustain an ESD level above 2000 V without extra process modification.

AB - A substrate-triggering technique, to increase the ESD robustness and to reduce the trigger voltage of the ESD protection device, is proposed to improve the ESD-protection efficiency of the input ESD protection circuit in deep-submicron CMOS technology. Through suitable substrate-triggering design on the device structure, this proposed input ESD protection circuit can successfully protect the thinner gate oxide (50 angstroms) of the input stage in a 0.25-μm CMOS technology and sustain an ESD level above 2000 V without extra process modification.

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U2 - 10.1109/ISCAS.1998.706879

DO - 10.1109/ISCAS.1998.706879

M3 - Conference article

AN - SCOPUS:0031641250

SN - 0271-4310

VL - 2

SP - 212

EP - 215

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

T2 - Proceedings of the 1998 IEEE International Symposium on Circuits and Systems, ISCAS. Part 5 (of 6)

Y2 - 31 May 1998 through 3 June 1998

ER -

Novel input ESD protection circuit with substrate-triggering technique in a 0.25-μm shallow-trench-isolation CMOS technology

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