Novel gate-all-around polycrystalline silicon nanowire memory device with HfAlO charge-trapping layer

Ko Hui Lee, Horng-Chih Lin*, Tiao Yuan Huang

*此作品的通信作者

研究成果: Article同行評審

10 引文 斯高帕斯(Scopus)

摘要

Gate-all-around (GAA) nanowire (NW) memory devices with a SiN- or Hf-based charge-trapping (CT) layer of the same thickness were studied in this work. The GAA NW devices were fabricated with planar thin-film transistors (TFTs) on the same substrate using a novel scheme without resorting to the use of advanced lithographic tools. Owing to their higher dielectric constant, the GAA NW devices with a HfO2 or HfAlO CT layer show greatly enhanced programming/erasing (P/E) efficiency as compared with those with a SiN CT layer. Furthermore, the incorporation of Al into the Hf-based dielectric increases the thermal stability of the CT layer, improving retention and endurance characteristics.

原文English
文章編號014001
期刊Japanese journal of applied physics
53
發行號1
DOIs
出版狀態Published - 1 1月 2014

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