Novel FFT processor with parallel-in-parallel-out in normal order

Hsiang Sheng Hu*, Hsiao Yun Chen, Shyh-Jye Jou

*此作品的通信作者

    研究成果: Conference contribution同行評審

    2 引文 斯高帕斯(Scopus)

    摘要

    A novel FFT processor that can provide parallel-in-parallel- out in normal order is proposed for high throughput required OFDM communication system, such as discrete Fourier transform (DFT)-based channel estimation in IEEE 802.16e. The hardware implementation results show the proposed 1024-point FFT architecture can achieve the throughput rate up to 1.28 G samples/sec and the execution time down to 7.3 us when working at 160 MHz. When working at the system required 83.3 MHz, it consumes 21.7 mW with 134474 gates (including memory) that occupy 0.471 mm 2 by using 90 nm, 1V CMOS process.

    原文English
    主出版物標題2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09
    頁面150-153
    頁數4
    DOIs
    出版狀態Published - 1 12月 2009
    事件2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09 - Hsinchu, Taiwan
    持續時間: 28 4月 200930 4月 2009

    出版系列

    名字2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09

    Conference

    Conference2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09
    國家/地區Taiwan
    城市Hsinchu
    期間28/04/0930/04/09

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