A novel four-phase dynamic CMOS logic is proposed, analysed and chip-tested. There are two circuit configurations in the new dynamic logic. One of these can completely get rid of the problems of charge sharing and clock skew, which are inherent in most of the dynamic circuits. The other, although it can only prevent the charge sharing problem, has a larger tolerance of the clock skew than the conventional four-phase precharge-discharge logic. The second configuration is more flexible in logic design than the first configuration. Both configurations use only three clock phases to form the four-phase dynamic circuits. After a brief analysis of the clock skew problem of the conventional four-phase logic, the new dynamic logic is introduced and the two circuit configurations are described. Then, the basic analysis on the device size design and performance evaluations of the new logic are given. A serial full adder was designed and implemented by a 3.5 /jm p-well CMOS process and the experimental results obtained from the test chip are presented.