Novel diode structures and ESD protection circuits in a 1.8-V 0.15-μm partially-depleted SOI salicided CMOS process

Ming-Dou Ker*, K. K. Hung, H. T.H. Tang, S. C. Huang, S. S. Chen, M. C. Wang

*此作品的通信作者

    研究成果: Paper同行評審

    15 引文 斯高帕斯(Scopus)

    摘要

    I-V characteristics, ESD robustness, and It2 of the gated and non-gated diode structures for ESD protection in a 0.15-μ-m partially-depleted silicon-on-insulator CMOS technology were studied and compared to that of Lubistor diode. A novel gate-triggered design on the power-rail ESD clamp circuit with the gated diodes in stacked configuration showed a higher ESD robustness and faster turn-on speed to effectively protect the devices of internal circuits.

    原文American English
    頁面91-96
    頁數6
    DOIs
    出版狀態Published - 7月 2001
    事件8th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA 2001) - Singapure, Singapore
    持續時間: 9 7月 200113 7月 2001

    Conference

    Conference8th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA 2001)
    國家/地區Singapore
    城市Singapure
    期間9/07/0113/07/01

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