摘要
I-V characteristics, ESD robustness, and It2 of the gated and non-gated diode structures for ESD protection in a 0.15-μ-m partially-depleted silicon-on-insulator CMOS technology were studied and compared to that of Lubistor diode. A novel gate-triggered design on the power-rail ESD clamp circuit with the gated diodes in stacked configuration showed a higher ESD robustness and faster turn-on speed to effectively protect the devices of internal circuits.
原文 | American English |
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頁面 | 91-96 |
頁數 | 6 |
DOIs | |
出版狀態 | Published - 7月 2001 |
事件 | 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA 2001) - Singapure, Singapore 持續時間: 9 7月 2001 → 13 7月 2001 |
Conference
Conference | 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA 2001) |
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國家/地區 | Singapore |
城市 | Singapure |
期間 | 9/07/01 → 13/07/01 |