Novel CMOS ESD/EOS protection circuit with full - SCR structures

Keyphrases

• Protection Circuit 100%
• ESD Protection Device 100%
• Negative Polarity 66%
• Positive Polarity 66%
• On chip 33%
• CMOS Technology 33%
• BiCMOS Technology 33%
• PMOS Device 33%
• NMOS Device 33%
• Effective Rate of Protection 33%
• Low Impedance 33%
• ESD Damage 33%
• ESD Current 33%
• RC Delay 33%
• Shunt Path 33%
• High-speed Applications 33%
• Polysilicon Resistor 33%
• Trigger Voltage 33%
• Layout Area 33%

Engineering

• Internals 100%
• Experimental Result 50%
• Nodes 50%
• Speed Application 50%
• Polysilicon 50%