Novel circuit-level model for gate oxide short and its testing method in SRAMs

Chen Wei Lin, Chia-Tso Chao, Chih Chieh Hsu

研究成果: Article同行評審

4 引文 斯高帕斯(Scopus)


Gate oxide short (GOS) has become a common defect for advanced technologies as the gate oxide thickness of a MOSFET is greatly reduced. The behavior of a GOS-impacted MOSFET is, however, complicated and difficult to be accurately modeled at the circuit level. In this paper, we first build a golden model of a GOS-impacted MOSFET by using technology CAD, and identify the limitation and inaccuracy of the previous GOS models. Next, we propose a novel circuit-level GOS model which provides a higher accuracy of its dc characteristics than any of the previous models and being is able to represent a minimum-size GOS-impacted MOSFET. In addition, the proposed model can fit the transient characteristics of a GOS by considering the capacitance change of the GOS-impacted MOSFET, which has not been discussed in previous work. Last, we utilize our proposed GOS model to develop a novel GOS test method for SRAMs, which can effectively detect the GOS defects usually escaped from the conventional IDDQ test and March test.

頁(從 - 到)1294-1307
期刊IEEE Transactions on Very Large Scale Integration (VLSI) Systems
出版狀態Published - 6月 2014


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