Novel 2-bit/cell wrapped-select-gate SONOS TFT memory using source-side injection for NOR-type flash array

Kuan Ti Wang; Fang Chang Hsueh; Yu Lun Lu; Tsung Yu Chiang; Yi Hong Wu; Chia Chun Liao; Li Chen Yen; Tien-Sheng Chao

doi:10.1109/LED.2012.2192090

Novel 2-bit/cell wrapped-select-gate SONOS TFT memory using source-side injection for NOR-type flash array

Kuan Ti Wang^*, Fang Chang Hsueh, Yu Lun Lu, Tsung Yu Chiang, Yi Hong Wu, Chia Chun Liao, Li Chen Yen, Tien-Sheng Chao

^*此作品的通信作者

電子物理學系

研究成果: Article › 同行評審

1 引文斯高帕斯（Scopus）

摘要

This letter is the first to successfully demonstrate the 2-bit/cell wrapped-selected-gate (WSG) SONOS thin-film transistor (TFT) memory using source-side injection (SSI). Because of the higher programming efficiency of SSI, a memory window of approximately 3 V can be easily achieved in 10 μ s and 30 ms for the program and erase modes, respectively. In addition, we performed an excellent 2-bit/cell distinguish margin for 3-V memory window in WSG-SONOS TFT memory. The optimal reliability of the endurance and data retention tests can be executed by adjusting the applied voltage appropriately.

原文	English
文章編號	6194261
頁（從 - 到）	839-841
頁數	3
期刊	IEEE Electron Device Letters
卷	33
發行號	6
DOIs	https://doi.org/10.1109/LED.2012.2192090
出版狀態	Published - 10 5月 2012

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10.1109/LED.2012.2192090

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引用此

@article{ee6f4ec8cc79414c9edd0b6371f4e171,

title = "Novel 2-bit/cell wrapped-select-gate SONOS TFT memory using source-side injection for NOR-type flash array",

abstract = "This letter is the first to successfully demonstrate the 2-bit/cell wrapped-selected-gate (WSG) SONOS thin-film transistor (TFT) memory using source-side injection (SSI). Because of the higher programming efficiency of SSI, a memory window of approximately 3 V can be easily achieved in 10 μ s and 30 ms for the program and erase modes, respectively. In addition, we performed an excellent 2-bit/cell distinguish margin for 3-V memory window in WSG-SONOS TFT memory. The optimal reliability of the endurance and data retention tests can be executed by adjusting the applied voltage appropriately.",

keywords = "Source-side injection (SSI), thin-film transistor memory, two-bit/cell, wrapped-selected-gate (WSG)-SONOS",

author = "Wang, {Kuan Ti} and Hsueh, {Fang Chang} and Lu, {Yu Lun} and Chiang, {Tsung Yu} and Wu, {Yi Hong} and Liao, {Chia Chun} and Yen, {Li Chen} and Tien-Sheng Chao",

year = "2012",

month = may,

day = "10",

doi = "10.1109/LED.2012.2192090",

language = "English",

volume = "33",

pages = "839--841",

journal = "IEEE Electron Device Letters",

issn = "0741-3106",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "6",

}

TY - JOUR

T1 - Novel 2-bit/cell wrapped-select-gate SONOS TFT memory using source-side injection for NOR-type flash array

AU - Wang, Kuan Ti

AU - Hsueh, Fang Chang

AU - Lu, Yu Lun

AU - Chiang, Tsung Yu

AU - Wu, Yi Hong

AU - Liao, Chia Chun

AU - Yen, Li Chen

AU - Chao, Tien-Sheng

PY - 2012/5/10

Y1 - 2012/5/10

N2 - This letter is the first to successfully demonstrate the 2-bit/cell wrapped-selected-gate (WSG) SONOS thin-film transistor (TFT) memory using source-side injection (SSI). Because of the higher programming efficiency of SSI, a memory window of approximately 3 V can be easily achieved in 10 μ s and 30 ms for the program and erase modes, respectively. In addition, we performed an excellent 2-bit/cell distinguish margin for 3-V memory window in WSG-SONOS TFT memory. The optimal reliability of the endurance and data retention tests can be executed by adjusting the applied voltage appropriately.

AB - This letter is the first to successfully demonstrate the 2-bit/cell wrapped-selected-gate (WSG) SONOS thin-film transistor (TFT) memory using source-side injection (SSI). Because of the higher programming efficiency of SSI, a memory window of approximately 3 V can be easily achieved in 10 μ s and 30 ms for the program and erase modes, respectively. In addition, we performed an excellent 2-bit/cell distinguish margin for 3-V memory window in WSG-SONOS TFT memory. The optimal reliability of the endurance and data retention tests can be executed by adjusting the applied voltage appropriately.

KW - Source-side injection (SSI)

KW - thin-film transistor memory

KW - two-bit/cell

KW - wrapped-selected-gate (WSG)-SONOS

UR - http://www.scopus.com/inward/record.url?scp=84861656619&partnerID=8YFLogxK

U2 - 10.1109/LED.2012.2192090

DO - 10.1109/LED.2012.2192090

M3 - Article

AN - SCOPUS:84861656619

VL - 33

SP - 839

EP - 841

JO - IEEE Electron Device Letters

JF - IEEE Electron Device Letters

SN - 0741-3106

IS - 6

M1 - 6194261

ER -

Novel 2-bit/cell wrapped-select-gate SONOS TFT memory using source-side injection for NOR-type flash array

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