Non-regression approach for the behavioral model generator in mixed-signal system verification

Ling Yen Song; Chun Wang; Chien-Nan Liu; Yun Jing Lin; Meng Jung Lee; Yu Lan Lo; Shu Yi Kao

doi:10.1109/VLSI-SoC.2017.8203462

Non-regression approach for the behavioral model generator in mixed-signal system verification

Ling Yen Song, Chun Wang, Chien-Nan Liu, Yun Jing Lin, Meng Jung Lee, Yu Lan Lo, Shu Yi Kao

電子研究所

研究成果: Conference contribution › 同行評審

3 引文斯高帕斯（Scopus）

摘要

Building the behavioral model for each analog circuit is an efficient approach for mixed-signal system verification. If an automatic model generator is available, it is useful for designers to reduce the extra efforts. Instead of modeling the relationship between circuit inputs and outputs directly, a divide and conquer approach is proposed in [8] to divide the circuit into several small building blocks and model the behavior of each block easily. Although the regression efforts have been greatly alleviated in this structure-based approach, the preparation of the training patterns is still a big issue. In this work, a different approach is proposed to build the behavioral model of each internal block in structure-based approach without regression. Therefore, no training patterns are required in the calibration process. As shown in the experimental results, the model accuracy is still kept in the proposed approach while the efficiency of behavioral model generator is greatly improved.

原文	English
主出版物標題	25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017 - Proceedings
發行者	IEEE Computer Society
ISBN（電子）	9781538628805
DOIs	https://doi.org/10.1109/VLSI-SoC.2017.8203462
出版狀態	Published - 13 12月 2017
事件	25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017 - Abu Dhabi, 阿拉伯聯合酋長國持續時間: 23 10月 2017 → 25 10月 2017

出版系列

名字	IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC
ISSN（列印）	2324-8432
ISSN（電子）	2324-8440

Conference

Conference	25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017
國家/地區	阿拉伯聯合酋長國
城市	Abu Dhabi
期間	23/10/17 → 25/10/17

存取文件

10.1109/VLSI-SoC.2017.8203462

其它文件與鏈接

Link to publication in Scopus

引用此

Song, L. Y., Wang, C., Liu, C.-N., Lin, Y. J., Lee, M. J., Lo, Y. L., & Kao, S. Y. (2017). Non-regression approach for the behavioral model generator in mixed-signal system verification. 於 25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017 - Proceedings 文章 8203462 (IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC). IEEE Computer Society. https://doi.org/10.1109/VLSI-SoC.2017.8203462

@inproceedings{d7a145e190634adbb4802a32b7d8e498,

title = "Non-regression approach for the behavioral model generator in mixed-signal system verification",

abstract = "Building the behavioral model for each analog circuit is an efficient approach for mixed-signal system verification. If an automatic model generator is available, it is useful for designers to reduce the extra efforts. Instead of modeling the relationship between circuit inputs and outputs directly, a divide and conquer approach is proposed in [8] to divide the circuit into several small building blocks and model the behavior of each block easily. Although the regression efforts have been greatly alleviated in this structure-based approach, the preparation of the training patterns is still a big issue. In this work, a different approach is proposed to build the behavioral model of each internal block in structure-based approach without regression. Therefore, no training patterns are required in the calibration process. As shown in the experimental results, the model accuracy is still kept in the proposed approach while the efficiency of behavioral model generator is greatly improved.",

keywords = "Behavioral model, Mixed-signal circuit, Model generator",

author = "Song, {Ling Yen} and Chun Wang and Chien-Nan Liu and Lin, {Yun Jing} and Lee, {Meng Jung} and Lo, {Yu Lan} and Kao, {Shu Yi}",

year = "2017",

month = dec,

day = "13",

doi = "10.1109/VLSI-SoC.2017.8203462",

language = "English",

series = "IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC",

publisher = "IEEE Computer Society",

booktitle = "25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017 - Proceedings",

address = "美國",

note = "25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017 ; Conference date: 23-10-2017 Through 25-10-2017",

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Song, LY, Wang, C, Liu, C-N, Lin, YJ, Lee, MJ, Lo, YL & Kao, SY 2017, Non-regression approach for the behavioral model generator in mixed-signal system verification. 於 25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017 - Proceedings., 8203462, IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC, IEEE Computer Society, 25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017, Abu Dhabi, 阿拉伯聯合酋長國, 23/10/17. https://doi.org/10.1109/VLSI-SoC.2017.8203462

Non-regression approach for the behavioral model generator in mixed-signal system verification. / Song, Ling Yen; Wang, Chun; Liu, Chien-Nan 等.
25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017 - Proceedings. IEEE Computer Society, 2017. 8203462 (IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC).

研究成果: Conference contribution › 同行評審

TY - GEN

T1 - Non-regression approach for the behavioral model generator in mixed-signal system verification

AU - Song, Ling Yen

AU - Wang, Chun

AU - Liu, Chien-Nan

AU - Lin, Yun Jing

AU - Lee, Meng Jung

AU - Lo, Yu Lan

AU - Kao, Shu Yi

PY - 2017/12/13

Y1 - 2017/12/13

N2 - Building the behavioral model for each analog circuit is an efficient approach for mixed-signal system verification. If an automatic model generator is available, it is useful for designers to reduce the extra efforts. Instead of modeling the relationship between circuit inputs and outputs directly, a divide and conquer approach is proposed in [8] to divide the circuit into several small building blocks and model the behavior of each block easily. Although the regression efforts have been greatly alleviated in this structure-based approach, the preparation of the training patterns is still a big issue. In this work, a different approach is proposed to build the behavioral model of each internal block in structure-based approach without regression. Therefore, no training patterns are required in the calibration process. As shown in the experimental results, the model accuracy is still kept in the proposed approach while the efficiency of behavioral model generator is greatly improved.

AB - Building the behavioral model for each analog circuit is an efficient approach for mixed-signal system verification. If an automatic model generator is available, it is useful for designers to reduce the extra efforts. Instead of modeling the relationship between circuit inputs and outputs directly, a divide and conquer approach is proposed in [8] to divide the circuit into several small building blocks and model the behavior of each block easily. Although the regression efforts have been greatly alleviated in this structure-based approach, the preparation of the training patterns is still a big issue. In this work, a different approach is proposed to build the behavioral model of each internal block in structure-based approach without regression. Therefore, no training patterns are required in the calibration process. As shown in the experimental results, the model accuracy is still kept in the proposed approach while the efficiency of behavioral model generator is greatly improved.

KW - Behavioral model

KW - Mixed-signal circuit

KW - Model generator

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M3 - Conference contribution

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T3 - IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC

BT - 25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017 - Proceedings

PB - IEEE Computer Society

T2 - 25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017

Y2 - 23 October 2017 through 25 October 2017

ER -

Song LY, Wang C, Liu CN, Lin YJ, Lee MJ, Lo YL 等. Non-regression approach for the behavioral model generator in mixed-signal system verification. 於 25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017 - Proceedings. IEEE Computer Society. 2017. 8203462. (IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC). doi: 10.1109/VLSI-SoC.2017.8203462

Non-regression approach for the behavioral model generator in mixed-signal system verification

摘要

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Conference

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