摘要
A simple and highly efficient successive-approximation registers (SAR) ADC realisation is proposed. It requires an opamp, a comparator and only three equal-valued capacitors. The proposed scheme is insensitive to the capacitor parasitics, and has a small capacitance spread. With an oversampled scheme, it also allows noise-shaping the remaining quantisation error. It is well-suited for low-frequency instrumentation and measurement applications, and for use in extended-counting ADCs.
原文 | English |
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頁(從 - 到) | 182-184 |
頁數 | 3 |
期刊 | Electronics Letters |
卷 | 49 |
發行號 | 3 |
DOIs | |
出版狀態 | Published - 31 1月 2013 |