TY - JOUR
T1 - New transient detection circuit for on-chip protection design against system-level electrical-transient disturbance
AU - Ker, Ming-Dou
AU - Yen, Cheng Cheng
PY - 2010/10/1
Y1 - 2010/10/1
N2 - A new transient detection circuit for on-chip protection design against system-level electrical-transient disturbance is proposed in this paper. The circuit function to detect positive or negative electrical transients under system-level electrostatic-discharge (ESD) and electrical-fast-transient (EFT) testing conditions has been investigated by HSPICE simulation and verified in silicon chip. The experimental results in a 0.18- μm complementary- metaloxidesemiconductor (CMOS) process have confirmed that the new proposed on-chip transient detection circuit can successfully memorize the occurrence of system-level electrical-transient disturbance events. The output of the proposed on-chip transient detection circuit can be used as a firmware index to execute the system recovery procedure. With hardware/firmware codesign, the transient disturbance immunity of microelectronic products equipped with CMOS integrated circuits under system-level ESD or EFT tests can be significantly improved.
AB - A new transient detection circuit for on-chip protection design against system-level electrical-transient disturbance is proposed in this paper. The circuit function to detect positive or negative electrical transients under system-level electrostatic-discharge (ESD) and electrical-fast-transient (EFT) testing conditions has been investigated by HSPICE simulation and verified in silicon chip. The experimental results in a 0.18- μm complementary- metaloxidesemiconductor (CMOS) process have confirmed that the new proposed on-chip transient detection circuit can successfully memorize the occurrence of system-level electrical-transient disturbance events. The output of the proposed on-chip transient detection circuit can be used as a firmware index to execute the system recovery procedure. With hardware/firmware codesign, the transient disturbance immunity of microelectronic products equipped with CMOS integrated circuits under system-level ESD or EFT tests can be significantly improved.
KW - Electrical-fast-transient (EFT) test
KW - electromagnetic compatibility
KW - electrostatic discharge (ESD)
KW - system-level ESD test
KW - transient detection circuit
UR - http://www.scopus.com/inward/record.url?scp=77956609647&partnerID=8YFLogxK
U2 - 10.1109/TIE.2009.2039456
DO - 10.1109/TIE.2009.2039456
M3 - Article
AN - SCOPUS:77956609647
SN - 0278-0046
VL - 57
SP - 3533
EP - 3543
JO - IEEE Transactions on Industrial Electronics
JF - IEEE Transactions on Industrial Electronics
IS - 10
M1 - 5406116
ER -