New Methodology for Evaluating Minority Carrier Lifetime for Process Assessment

K. Kakushima, T. Hoshii, M. Watanabe, N. Shizyo, K. Furukawa, T. Saraya, T. Takakura, K. Itou, M. Fukui, S. Suzuki, K. Takeuchi, I. Muneta, H. Wakabayashi, Y. Numasawa, A. Ogura, S. Nishizawa, K. Tsutsui, T. Hiramoto, H. Ohashi, H. Iwai

研究成果: Conference contribution同行評審

3 引文 斯高帕斯(Scopus)

摘要

A new methodology to evaluate the process temperature dependence of the minority carrier lifetime has been developed. A TEG layout with p+-stripes on an n-Si substrate was designed. When all the p+n junctions are made forward, the minority carrier diffusion current flows one dimensionally into the substrate. On the other hand, for making only the one center p+n junction forward, the current spreads laterally and flows cylindrically into the substrate. By the difference in the flow path of the minority carrier diffusion, we can successfully extract the minority carrier lifetime. We applied this methodology to the evaluation of the minority carrier lifetime depending on process temperatures and confirmed the lifetime degradation for high temperature process.

原文English
主出版物標題2018 IEEE Symposium on VLSI Circuits, VLSI Circuits 2018
發行者Institute of Electrical and Electronics Engineers Inc.
頁面105-106
頁數2
ISBN(電子)9781538667002
DOIs
出版狀態Published - 22 十月 2018
事件32nd IEEE Symposium on VLSI Circuits, VLSI Circuits 2018 - Honolulu, United States
持續時間: 18 六月 201822 六月 2018

出版系列

名字IEEE Symposium on VLSI Circuits, Digest of Technical Papers
2018-June

Conference

Conference32nd IEEE Symposium on VLSI Circuits, VLSI Circuits 2018
國家/地區United States
城市Honolulu
期間18/06/1822/06/18

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