New layout scheme to improve ESD robustness of I/O buffers in fully-silicided CMOS process
- Ming-Dou Ker*
- , Wen Yi Chen
- , Wuu Trong Shieh
- , I. Ju Wei
*此作品的通信作者
研究成果: Conference contribution › 同行評審
2
引文
斯高帕斯(Scopus)