New layout scheme to improve ESD robustness of I/O buffers in fully-silicided CMOS process

  • Ming-Dou Ker*
  • , Wen Yi Chen
  • , Wuu Trong Shieh
  • , I. Ju Wei
  • *此作品的通信作者

    研究成果: Conference contribution同行評審

    2 引文 斯高帕斯(Scopus)

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