@inproceedings{7a046545f9364e34b8c6f2398957569c,
title = "New layout scheme to improve ESD robustness of I/O buffers in fully-silicided CMOS process",
abstract = "Silicidation used in CMOS processes has been reported to result in substantial degradation on ESD robustness of CMOS devices. In this work, a new ballasting layout scheme for fully-silicided I/O buffer is proposed to enhance its ESD robustness. Experimental results from real IC products have confirmed that the new ballasting layout scheme can successfully increase HBM ESD robustness of fully-silicided I/O buffers from 1.5kV to 7kV without using the additional silicide-blocking mask.",
author = "Ming-Dou Ker and Chen, {Wen Yi} and Shieh, {Wuu Trong} and Wei, {I. Ju}",
year = "2009",
month = nov,
language = "English",
isbn = "1585371750",
series = "Electrical Overstress/Electrostatic Discharge Symposium Proceedings",
booktitle = "Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2009, EOS/ESD 2009",
note = "Electrical Overstress/Electrostatic Discharge Symposium 2009, EOS/ESD 2009 ; Conference date: 30-08-2009 Through 04-09-2009",
}