Silicidation used in CMOS processes has been reported to result in substantial degradation on ESD robustness of CMOS devices. In this work, a new ballasting layout scheme for fully-silicided I/O buffer is proposed to enhance its ESD robustness. Experimental results from real IC products have confirmed that the new ballasting layout scheme can successfully increase HBM ESD robustness of fully-silicided I/O buffers from 1.5kV to 7kV without using the additional silicide-blocking mask.
|主出版物標題||Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2009, EOS/ESD 2009|
|出版狀態||Published - 11月 2009|
|事件||Electrical Overstress/Electrostatic Discharge Symposium 2009, EOS/ESD 2009 - Anaheim, CA, United States|
持續時間: 30 8月 2009 → 4 9月 2009
|名字||Electrical Overstress/Electrostatic Discharge Symposium Proceedings|
|Conference||Electrical Overstress/Electrostatic Discharge Symposium 2009, EOS/ESD 2009|
|期間||30/08/09 → 4/09/09|