New layout scheme to improve ESD robustness of I/O buffers in fully-silicided CMOS process

Ming-Dou Ker*, Wen Yi Chen, Wuu Trong Shieh, I. Ju Wei

*此作品的通信作者

    研究成果: Conference contribution同行評審

    2 引文 斯高帕斯(Scopus)

    摘要

    Silicidation used in CMOS processes has been reported to result in substantial degradation on ESD robustness of CMOS devices. In this work, a new ballasting layout scheme for fully-silicided I/O buffer is proposed to enhance its ESD robustness. Experimental results from real IC products have confirmed that the new ballasting layout scheme can successfully increase HBM ESD robustness of fully-silicided I/O buffers from 1.5kV to 7kV without using the additional silicide-blocking mask.

    原文English
    主出版物標題Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2009, EOS/ESD 2009
    出版狀態Published - 11月 2009
    事件Electrical Overstress/Electrostatic Discharge Symposium 2009, EOS/ESD 2009 - Anaheim, CA, 美國
    持續時間: 30 8月 20094 9月 2009

    出版系列

    名字Electrical Overstress/Electrostatic Discharge Symposium Proceedings
    ISSN(列印)0739-5159

    Conference

    ConferenceElectrical Overstress/Electrostatic Discharge Symposium 2009, EOS/ESD 2009
    國家/地區美國
    城市Anaheim, CA
    期間30/08/094/09/09

    指紋

    深入研究「New layout scheme to improve ESD robustness of I/O buffers in fully-silicided CMOS process」主題。共同形成了獨特的指紋。

    引用此