New layout design for submicron CMOS output transistors to improve driving capability and ESD robustness in per unit layout area

Ming-Dou Ker; Tung Yang Chen; Chung-Yu Wu

doi:10.1109/IPFA.1997.638152

New layout design for submicron CMOS output transistors to improve driving capability and ESD robustness in per unit layout area

Ming-Dou Ker^*, Tung Yang Chen, Chung-Yu Wu

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研究成果: Paper › 同行評審

1 引文斯高帕斯（Scopus）

摘要

Three new device structures to effectively reduce the layout area of CMOS output buffers with higher driving capability and better ESD reliability are proposed. With theoretical calculation and experimental verification, both the higher output driving/sinking capability and the stronger ESD robustness of CMOS output buffers can be practically achieved by the new proposed layout designs within smaller layout area. The output devices assembled by a plurality of the proposed basic layout cells have a lower ploy-gate resistance and a smaller drain capacitance than that by the traditional finger-type layout.

原文	English
頁面	103-108
頁數	6
DOIs	https://doi.org/10.1109/IPFA.1997.638152
出版狀態	Published - 1 12月 1997
事件	Proceedings of the 1997 6th International Symposium on the Physical & Failure Analysis of Integrated Circuits, IPFA - Singapore, Singapore 持續時間: 21 7月 1997 → 25 7月 1997

Conference

Conference	Proceedings of the 1997 6th International Symposium on the Physical & Failure Analysis of Integrated Circuits, IPFA
城市	Singapore, Singapore
期間	21/07/97 → 25/07/97

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10.1109/IPFA.1997.638152

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Ker, M.-D., Chen, T. Y., & Wu, C.-Y. (1997). New layout design for submicron CMOS output transistors to improve driving capability and ESD robustness in per unit layout area. 103-108. 論文發表於 Proceedings of the 1997 6th International Symposium on the Physical & Failure Analysis of Integrated Circuits, IPFA, Singapore, Singapore. https://doi.org/10.1109/IPFA.1997.638152

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title = "New layout design for submicron CMOS output transistors to improve driving capability and ESD robustness in per unit layout area",

abstract = "Three new device structures to effectively reduce the layout area of CMOS output buffers with higher driving capability and better ESD reliability are proposed. With theoretical calculation and experimental verification, both the higher output driving/sinking capability and the stronger ESD robustness of CMOS output buffers can be practically achieved by the new proposed layout designs within smaller layout area. The output devices assembled by a plurality of the proposed basic layout cells have a lower ploy-gate resistance and a smaller drain capacitance than that by the traditional finger-type layout.",

author = "Ming-Dou Ker and Chen, {Tung Yang} and Chung-Yu Wu",

year = "1997",

month = dec,

day = "1",

doi = "10.1109/IPFA.1997.638152",

language = "English",

pages = "103--108",

note = "Proceedings of the 1997 6th International Symposium on the Physical & Failure Analysis of Integrated Circuits, IPFA ; Conference date: 21-07-1997 Through 25-07-1997",

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Ker, M-D, Chen, TY & Wu, C-Y 1997, 'New layout design for submicron CMOS output transistors to improve driving capability and ESD robustness in per unit layout area', 論文發表於 Proceedings of the 1997 6th International Symposium on the Physical & Failure Analysis of Integrated Circuits, IPFA, Singapore, Singapore, 21/07/97 - 25/07/97 頁 103-108. https://doi.org/10.1109/IPFA.1997.638152

New layout design for submicron CMOS output transistors to improve driving capability and ESD robustness in per unit layout area. / Ker, Ming-Dou; Chen, Tung Yang; Wu, Chung-Yu.
1997. 103-108 論文發表於 Proceedings of the 1997 6th International Symposium on the Physical & Failure Analysis of Integrated Circuits, IPFA, Singapore, Singapore.

研究成果: Paper › 同行評審

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AB - Three new device structures to effectively reduce the layout area of CMOS output buffers with higher driving capability and better ESD reliability are proposed. With theoretical calculation and experimental verification, both the higher output driving/sinking capability and the stronger ESD robustness of CMOS output buffers can be practically achieved by the new proposed layout designs within smaller layout area. The output devices assembled by a plurality of the proposed basic layout cells have a lower ploy-gate resistance and a smaller drain capacitance than that by the traditional finger-type layout.

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New layout design for submicron CMOS output transistors to improve driving capability and ESD robustness in per unit layout area

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