New layout arrangement to improve ESD robustness of large-array high-voltage nLDMOS

Wen Yi Chen*, Ming-Dou Ker

*此作品的通信作者

    研究成果: Article同行評審

    26 引文 斯高帕斯(Scopus)

    摘要

    In high-voltage applications, large-array n-channel lateral DMOS (LA-nLDMOS) is usually required to provide high driving capability. However, without following the foundry-suggested electrostatic discharge (ESD) design guidelines in order to reduce total layout area, LA-nLDMOS is easily damaged once the parasitic bipolar junction transistor is triggered under ESD stresses. Accordingly, the bipolar triggering of LA-nLDMOS usually limits the ESD robustness of LA-nLDMOS, particularly in the open-drain structure. In this letter, a new layout arrangement for LA-nLDMOS has been proposed to suppress the bipolar triggering under ESD stresses. Measurement results in a 0.5-μm 16-V bipolar CMOS DMOS process have confirmed that the new proposed layout arrangement can successfully increase the human-body-model ESD level of the LA-nLDMOS with effective width of 3000 μm from the original 0.75 kV up to 2.75 kV.

    原文English
    文章編號5357417
    頁(從 - 到)159-161
    頁數3
    期刊IEEE Electron Device Letters
    31
    發行號2
    DOIs
    出版狀態Published - 1 二月 2010

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