New experimental methodology to extract compact layout rules for latchup prevention in bulk CMOS IC's

Ming-Dou Ker; Wen Yu Lo; Chung-Yu Wu

doi:10.1109/CICC.1999.777261

New experimental methodology to extract compact layout rules for latchup prevention in bulk CMOS IC's

Ming-Dou Ker^*, Wen Yu Lo, Chung-Yu Wu

^*此作品的通信作者

電子研究所

研究成果: Conference contribution › 同行評審

8 引文斯高帕斯（Scopus）

摘要

A new experimental methodology to find the compact layout rules on guard rings is proposed to increase latchup immunity of bulk CMOS IC's. The layout rules are extracted from the experimental testchips with the latchup sensors and different drawing spacings. A new latchup prevention design with additional internal guard rings between the I/O cells and the internal circuits is first investigated in the fabricated experimental testchips. Through detailed experimental verification including temperature effect, one set of compact layout rules has been established to save the chip size of the pad-limited CMOS IC's but still with enough latchup immunity in a 0.5-μm bulk CMOS technology.

原文	English
主出版物標題	Proceedings of the Custom Integrated Circuits Conference
發行者	IEEE
頁面	143-146
頁數	4
ISBN（列印）	0780354443
DOIs	https://doi.org/10.1109/CICC.1999.777261
出版狀態	Published - 1 1月 1999
事件	Proceedings of the 1999 21st IEEE Annual Custom Integrated Circuits Conference, CICC '99 - San Diego, CA, USA 持續時間: 16 5月 1999 → 19 5月 1999

出版系列

名字	Proceedings of the Custom Integrated Circuits Conference
ISSN（列印）	0886-5930

Conference

Conference	Proceedings of the 1999 21st IEEE Annual Custom Integrated Circuits Conference, CICC '99
城市	San Diego, CA, USA
期間	16/05/99 → 19/05/99

存取文件

10.1109/CICC.1999.777261

其它文件與鏈接

Link to publication in Scopus

引用此

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title = "New experimental methodology to extract compact layout rules for latchup prevention in bulk CMOS IC's",

abstract = "A new experimental methodology to find the compact layout rules on guard rings is proposed to increase latchup immunity of bulk CMOS IC's. The layout rules are extracted from the experimental testchips with the latchup sensors and different drawing spacings. A new latchup prevention design with additional internal guard rings between the I/O cells and the internal circuits is first investigated in the fabricated experimental testchips. Through detailed experimental verification including temperature effect, one set of compact layout rules has been established to save the chip size of the pad-limited CMOS IC's but still with enough latchup immunity in a 0.5-μm bulk CMOS technology.",

author = "Ming-Dou Ker and Lo, {Wen Yu} and Chung-Yu Wu",

year = "1999",

month = jan,

day = "1",

doi = "10.1109/CICC.1999.777261",

language = "English",

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series = "Proceedings of the Custom Integrated Circuits Conference",

publisher = "IEEE",

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note = "Proceedings of the 1999 21st IEEE Annual Custom Integrated Circuits Conference, CICC '99 ; Conference date: 16-05-1999 Through 19-05-1999",

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Ker, M-D, Lo, WY & Wu, C-Y 1999, New experimental methodology to extract compact layout rules for latchup prevention in bulk CMOS IC's. 於 Proceedings of the Custom Integrated Circuits Conference. Proceedings of the Custom Integrated Circuits Conference, IEEE, 頁 143-146, Proceedings of the 1999 21st IEEE Annual Custom Integrated Circuits Conference, CICC '99, San Diego, CA, USA, 16/05/99. https://doi.org/10.1109/CICC.1999.777261

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AU - Wu, Chung-Yu

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N2 - A new experimental methodology to find the compact layout rules on guard rings is proposed to increase latchup immunity of bulk CMOS IC's. The layout rules are extracted from the experimental testchips with the latchup sensors and different drawing spacings. A new latchup prevention design with additional internal guard rings between the I/O cells and the internal circuits is first investigated in the fabricated experimental testchips. Through detailed experimental verification including temperature effect, one set of compact layout rules has been established to save the chip size of the pad-limited CMOS IC's but still with enough latchup immunity in a 0.5-μm bulk CMOS technology.

AB - A new experimental methodology to find the compact layout rules on guard rings is proposed to increase latchup immunity of bulk CMOS IC's. The layout rules are extracted from the experimental testchips with the latchup sensors and different drawing spacings. A new latchup prevention design with additional internal guard rings between the I/O cells and the internal circuits is first investigated in the fabricated experimental testchips. Through detailed experimental verification including temperature effect, one set of compact layout rules has been established to save the chip size of the pad-limited CMOS IC's but still with enough latchup immunity in a 0.5-μm bulk CMOS technology.

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PB - IEEE

T2 - Proceedings of the 1999 21st IEEE Annual Custom Integrated Circuits Conference, CICC '99

Y2 - 16 May 1999 through 19 May 1999

ER -

New experimental methodology to extract compact layout rules for latchup prevention in bulk CMOS IC's

摘要

出版系列

Conference

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其它文件與鏈接

指紋

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