NEW DRY RECESS ETCHING TECHNOLOGY FOR GAAS DIGITAL ICS.

F. J. Ryan*, Mau-Chung Chang, R. P. Vahrenkamp, D. A. Williams, W. P. Fleming, C. G. Kirkpatrick

*此作品的通信作者

    研究成果: Paper同行評審

    3 引文 斯高帕斯(Scopus)

    摘要

    A dry recess technology that is compatible with a self-aligned enhancement/depletion (E/D) MESFET IC process on 3-in GaAs wafers for gate lengths 1 mu m and below is presented. A self-limiting gate recess process called SLICE is used to maintain voltage threshold control and across-wafer uniformity of E-MESFETs. Using the dry gate recess E-MESFET, the authors have successfully fabricated state-of-the-art high transconductance E-MESFETs, E/D ring oscillators and E/D DCFL (direct coupled FET logic) dividers.

    原文English
    頁面45-48
    頁數4
    出版狀態Published - 1 12月 1985

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