New design technology for EEPROM memory cells with 10 million write/erase cycling endurance

T. Endoh*, Shirota Riichiro, Y. Tanaka, R. Nakayama, R. Kirisawa, S. Aritome, F. Masuoka

*此作品的通信作者

研究成果: Conference article同行評審

6 引文 斯高帕斯(Scopus)

摘要

The authors describe a novel design technology for improving the write/erase cycling endurance characteristics for EEPROM (electrically erasable programmable ROM) memory cells with self-aligned double polycrystalline silicon stacked structure. In this device, the source n+ region is located within the depletion region of the surface channel area when high voltage is applied to the drain with the source left floating. It is confirmed experimentally that the endurance of the newly designed memory cell using an 0.5-μm design rule can be more than 107 write/erase cycles. This memory cell has superior potential for application to 64-Mb flash or 4-Mb full-featured EEPROMs.

原文English
頁(從 - 到)599-602
頁數4
期刊Technical Digest - International Electron Devices Meeting
DOIs
出版狀態Published - 1 12月 1989
事件1989 International Electron Devices Meeting - Technical Digest - Washington, DC, USA
持續時間: 3 12月 19896 12月 1989

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