The authors describe a novel design technology for improving the write/erase cycling endurance characteristics for EEPROM (electrically erasable programmable ROM) memory cells with self-aligned double polycrystalline silicon stacked structure. In this device, the source n+ region is located within the depletion region of the surface channel area when high voltage is applied to the drain with the source left floating. It is confirmed experimentally that the endurance of the newly designed memory cell using an 0.5-μm design rule can be more than 107 write/erase cycles. This memory cell has superior potential for application to 64-Mb flash or 4-Mb full-featured EEPROMs.
|頁（從 - 到）||599-602|
|期刊||Technical Digest - International Electron Devices Meeting|
|出版狀態||Published - 1 12月 1989|
|事件||1989 International Electron Devices Meeting - Technical Digest - Washington, DC, USA|
持續時間: 3 12月 1989 → 6 12月 1989