New design on 2VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65nm CMOS process

Chih Ting Yeh; Ming-Dou Ker

doi:10.1109/VLSI-DAT.2012.6212606

New design on 2VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65nm CMOS process

Chih Ting Yeh^*, Ming-Dou Ker

^*此作品的通信作者

研究成果: Conference contribution › 同行評審

3 引文斯高帕斯（Scopus）

摘要

A 2VDD-tolerant power-rail electrostatic discharge (ESD) clamp circuit with only thin gate oxide 1V devices and silicon-controlled rectifier (SCR) as main ESD clamp device has been proposed and verified in a 65nm CMOS process. The proposed power-rail ESD clamp circuit has an ultra-low standby leakage current by reducing the voltage drop across the gate oxide of the devices in the ESD detection circuit. From the measured results, the proposed design with SCR dimension of 50m in width can achieve 6.5kV human-body-model (HBM), 300V machine-model (MM) ESD levels, and an ultra-low standby leakage current of 34.1nA at room temperature under the normal circuit operating condition with 1.8V bias.

原文	English
主出版物標題	2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers
DOIs	https://doi.org/10.1109/VLSI-DAT.2012.6212606
出版狀態	Published - 25 7月 2012
事件	2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Hsinchu, Taiwan 持續時間: 23 4月 2012 → 25 4月 2012

出版系列

名字	2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers

Conference

Conference	2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012
國家/地區	Taiwan
城市	Hsinchu
期間	23/04/12 → 25/04/12

存取文件

10.1109/VLSI-DAT.2012.6212606

其它文件與鏈接

Link to publication in Scopus

引用此

Yeh, C. T., & Ker, M.-D. (2012). New design on 2VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65nm CMOS process. 於 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers 文章 6212606 (2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers). https://doi.org/10.1109/VLSI-DAT.2012.6212606

Yeh, Chih Ting ; Ker, Ming-Dou. / New design on 2VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65nm CMOS process. 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers. 2012. (2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers).

@inproceedings{fa2383961c9448e0a190cc4660ccfca5,

title = "New design on 2VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65nm CMOS process",

abstract = "A 2VDD-tolerant power-rail electrostatic discharge (ESD) clamp circuit with only thin gate oxide 1V devices and silicon-controlled rectifier (SCR) as main ESD clamp device has been proposed and verified in a 65nm CMOS process. The proposed power-rail ESD clamp circuit has an ultra-low standby leakage current by reducing the voltage drop across the gate oxide of the devices in the ESD detection circuit. From the measured results, the proposed design with SCR dimension of 50m in width can achieve 6.5kV human-body-model (HBM), 300V machine-model (MM) ESD levels, and an ultra-low standby leakage current of 34.1nA at room temperature under the normal circuit operating condition with 1.8V bias.",

author = "Yeh, {Chih Ting} and Ming-Dou Ker",

year = "2012",

month = jul,

day = "25",

doi = "10.1109/VLSI-DAT.2012.6212606",

language = "English",

isbn = "9781457720819",

series = "2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers",

booktitle = "2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers",

note = "2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 ; Conference date: 23-04-2012 Through 25-04-2012",

}

Yeh, CT & Ker, M-D 2012, New design on 2VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65nm CMOS process. 於 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers., 6212606, 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers, 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012, Hsinchu, Taiwan, 23/04/12. https://doi.org/10.1109/VLSI-DAT.2012.6212606

New design on 2VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65nm CMOS process. / Yeh, Chih Ting; Ker, Ming-Dou.
2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers. 2012. 6212606 (2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers).

研究成果: Conference contribution › 同行評審

TY - GEN

T1 - New design on 2VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65nm CMOS process

AU - Yeh, Chih Ting

AU - Ker, Ming-Dou

PY - 2012/7/25

Y1 - 2012/7/25

N2 - A 2VDD-tolerant power-rail electrostatic discharge (ESD) clamp circuit with only thin gate oxide 1V devices and silicon-controlled rectifier (SCR) as main ESD clamp device has been proposed and verified in a 65nm CMOS process. The proposed power-rail ESD clamp circuit has an ultra-low standby leakage current by reducing the voltage drop across the gate oxide of the devices in the ESD detection circuit. From the measured results, the proposed design with SCR dimension of 50m in width can achieve 6.5kV human-body-model (HBM), 300V machine-model (MM) ESD levels, and an ultra-low standby leakage current of 34.1nA at room temperature under the normal circuit operating condition with 1.8V bias.

AB - A 2VDD-tolerant power-rail electrostatic discharge (ESD) clamp circuit with only thin gate oxide 1V devices and silicon-controlled rectifier (SCR) as main ESD clamp device has been proposed and verified in a 65nm CMOS process. The proposed power-rail ESD clamp circuit has an ultra-low standby leakage current by reducing the voltage drop across the gate oxide of the devices in the ESD detection circuit. From the measured results, the proposed design with SCR dimension of 50m in width can achieve 6.5kV human-body-model (HBM), 300V machine-model (MM) ESD levels, and an ultra-low standby leakage current of 34.1nA at room temperature under the normal circuit operating condition with 1.8V bias.

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M3 - Conference contribution

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SN - 9781457720819

T3 - 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers

BT - 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers

T2 - 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012

Y2 - 23 April 2012 through 25 April 2012

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Yeh CT, Ker MD. New design on 2VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65nm CMOS process. 於 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers. 2012. 6212606. (2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers). doi: 10.1109/VLSI-DAT.2012.6212606

New design on 2VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65nm CMOS process

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