TY - JOUR
T1 - New chaotic key-based design for image encryption and decryption
AU - Yen, Jui Cheng
AU - Guo, Jiun-In
PY - 2000/1/1
Y1 - 2000/1/1
N2 - In this paper, an image encryption/decryption algorithm and its VLSI architecture are proposed. According to a chaotic binary sequence, the gray level of each pixel is XORed or XNORed bit-by-bit to one of the two predetermined keys. Its features are as follows: 1) low computational complexity, 2) high security, and 3) no distortion. In order to implement the algorithm, its VLSI architecture with low hardware cost, high computing speed, and high hardware utilization efficiency is also designed. Moreover, the architecture of integrating the scheme with MPEG2 is proposed. Finally, simulation results are included to demonstrate its effectiveness.
AB - In this paper, an image encryption/decryption algorithm and its VLSI architecture are proposed. According to a chaotic binary sequence, the gray level of each pixel is XORed or XNORed bit-by-bit to one of the two predetermined keys. Its features are as follows: 1) low computational complexity, 2) high security, and 3) no distortion. In order to implement the algorithm, its VLSI architecture with low hardware cost, high computing speed, and high hardware utilization efficiency is also designed. Moreover, the architecture of integrating the scheme with MPEG2 is proposed. Finally, simulation results are included to demonstrate its effectiveness.
UR - http://www.scopus.com/inward/record.url?scp=0033681472&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2000.858685
DO - 10.1109/ISCAS.2000.858685
M3 - Conference article
AN - SCOPUS:0033681472
SN - 0271-4310
VL - 4
JO - Proceedings - IEEE International Symposium on Circuits and Systems
JF - Proceedings - IEEE International Symposium on Circuits and Systems
T2 - Proceedings of the IEEE 2000 International Symposium on Circuits and Systems
Y2 - 28 May 2000 through 31 May 2000
ER -