New autosizing algorithm for CMOS combinational logic circuits

Chung-Yu Wu*, Jen Sheng Hwang

*此作品的通信作者

    研究成果: Paper同行評審

    2 引文 斯高帕斯(Scopus)

    摘要

    A sizing and constrained optimization algorithm for CMOS (complementary metal-oxide semiconductor) combinational logic circuits is presented. A constrained optimization problem is first transformed to a Lagrange multiplier form with a suitable cost function. Various techniques are applied to choose optimization variables, initial guess, and optimization direction and to reduce the occurrence of local minimum. As an example, the algorithm is applied to the minimization of power dissipation with a fixed delay constraint for the sizing of CMOS (complementary metal-oxide semiconductor) combinational logic circuits. It is shown that due to the proper choice of optimization variables, initial guess values, and optimization directions and the reduced occurrence of local minimum in the algorithm, the efficiency of the sizing and optimization are improved. The algorithm can be applied to many other circuit optimization problems with constraints.

    原文English
    頁面242-246
    頁數5
    DOIs
    出版狀態Published - 1 12月 1989
    事件International Symposium on VLSI Technology, Systems and Applications - Proceedings of Technical Papers - Taipei, Taiwan
    持續時間: 17 5月 198919 5月 1989

    Conference

    ConferenceInternational Symposium on VLSI Technology, Systems and Applications - Proceedings of Technical Papers
    城市Taipei, Taiwan
    期間17/05/8919/05/89

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