This paper presents a low computational complexity hardware-oriented neuromorphic pitch based noise reduction (NR) algorithm and hardware implementation for monosyllable hearing aid system applications. The proposed NR design consists of a pitch-based voice activity detector (pitch-based VAD) for speech detection and a neuromorphic noise attenuator for speech enhancement. The pitch-based VAD is developed on ANSI S1.11 based filter bank architecture and employs the characteristics of monosyllable and nonlinear energy operator (NEO) to improve the accuracy of VAD. The neuromorphic noise attenuator reduces the background noise by using the characteristics of human hearing system and the clues of speech. Simulation results show that the proposed algorithm has better SNR and PESQ performance than other non-pitch based NR algorithms in non-stationary background noise environments. Compared with multiband (mband) spectral subtraction and minimum mean square error (mmse) algorithms, the computational complexity of the proposed algorithm can save 90% computational complexity. The hardware implementation consumes 47.74 μ W at 0.5 V operation with 65 nm HVT standard cell library.
|頁（從 - 到）||463-475|
|期刊||IEEE Transactions on Circuits and Systems I: Regular Papers|
|出版狀態||Published - 1 2月 2014|