Nearly Ideal Subthreshold Swing in Monolayer MoS Top-Gate nFETs with Scaled EOT of 1 nm

Tsung En Lee*, Yuan Chun Su, Bo Jiun Lin, Yi Xuan Chen, Wei Sheng Yun, Po Hsun Ho, Jer Fu Wang, Sheng Kai Su, Chen Feng Hsu, Po Sen Mao, Yu Cheng Chang, Chao Hsin Chien, Bo Heng Liu, Chien Ying Su, Chi Chung Kei, Han Wang, H. S. Philip Wong, T. Y. Lee, Wen Hao Chang, Chao Ching ChengIuliana P. Radu

*此作品的通信作者

研究成果: Conference contribution同行評審

3 引文 斯高帕斯(Scopus)

摘要

Transistor scaling enabled by gate length scaling requires EOT scaling to less than 1 nm thickness [1]. This work successfully integrates Hf-based ALD higher-k dielectrics with CVD-grown monolayer (1L) MoS2 to build top-gate nFET with EOT 1 nm with nearly ideal subthreshold swing of 68 mV/dec. The gate stack described here achieves a high varepsilon-{ mathrm{e} mathrm{f} mathrm{f}} 13.53, a large mathrm{E}-{ mathrm{B} mathrm{D}} 12.4MV/cm, and excellent leakage current density. This is a remarkable performance among reported gate dielectrics on the transition metal dichalcogenides (TMDs) on which it is notoriously difficult to deposit a pinhole-free dielectric.

原文English
主出版物標題2022 International Electron Devices Meeting, IEDM 2022
發行者Institute of Electrical and Electronics Engineers Inc.
頁面741-744
頁數4
ISBN(電子)9781665489591
DOIs
出版狀態Published - 2022
事件2022 International Electron Devices Meeting, IEDM 2022 - San Francisco, United States
持續時間: 3 12月 20227 12月 2022

出版系列

名字Technical Digest - International Electron Devices Meeting, IEDM
2022-December
ISSN(列印)0163-1918

Conference

Conference2022 International Electron Devices Meeting, IEDM 2022
國家/地區United States
城市San Francisco
期間3/12/227/12/22

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