Near-threshold all-digital PLL with dynamic voltage scaling power management

C. W. Chang*, K. Y. Chang, Y. H. Chu, Shyh-Jye Jou

*此作品的通信作者

研究成果: Article同行評審

6 引文 斯高帕斯(Scopus)

摘要

A near-threshold all-digital phase-locked loop (ADPLL) with a power management unit (PMU) is presented to make the proposed ADPLL work reliably across variations and power consumption as well is reduced. When operated under near-threshold condition from 0.52 to 0.58 V V DD , the gated digitally controlled oscillator frequency range is from 90.8 to 245.7 MHz. When the ADPLL is operated at 0.52 V V DD , a lock-in time of 9.5 μs at 100 MHz output clock frequency is measured with an rms period jitter of 0.17% UI. With the PMU, the ADPLL power reduction at 130 MHz output frequency is 39% and the buck converter power consumption is nearly 30 μW. Consequently, the proposed ADPLL with PMU is suitable to eventdriven or low-voltage applications.

原文English
頁(從 - 到)109-111
頁數3
期刊Electronics Letters
52
發行號2
DOIs
出版狀態Published - 21 1月 2016

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