NCTUcell: A DDA-aware cell library generator for FinFET structure with implicitly adjustable grid map

Yih Lang Li, Shih Ting Lin, Shinichi Nishizawa, Hong Yan Su, Ming Jie Fong, Oscar Chen, Hidetoshi Onodera

研究成果: Conference contribution同行評審

12 引文 斯高帕斯(Scopus)

摘要

For 7nm technology node, cell placement with drain-to-drain abutment (DDA) requires additional filler cells, increasing placement area. This is the first work to fully automatically synthesize a DDA-aware cell library with optimized number of drains on cell boundary based on ASAP 7nm PDK. We propose a DDA-aware dynamic programming based transistor placement. Previous works ignore the use of M0 layer in cell routing. We firstly propose an ILP-based M0 routing planning. With M0 routing, the congestion of M1 routing can be reduced and the pin accessibility can be improved due to the diminished use of M2 routing. To improve the routing resource utilization, we propose an implicitly adjustable grid map, making the maze routing able to explore more routing solutions. Experimental results show that block placement using the DDA-aware cell library requires less filler cells than that using traditional cell library by 70.9%, which achieves a block area reduction rate of 5.7%.

原文English
主出版物標題Proceedings of the 56th Annual Design Automation Conference 2019, DAC 2019
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781450367257
DOIs
出版狀態Published - 2 6月 2019
事件56th Annual Design Automation Conference, DAC 2019 - Las Vegas, United States
持續時間: 2 6月 20196 6月 2019

出版系列

名字Proceedings - Design Automation Conference
ISSN(列印)0738-100X

Conference

Conference56th Annual Design Automation Conference, DAC 2019
國家/地區United States
城市Las Vegas
期間2/06/196/06/19

指紋

深入研究「NCTUcell: A DDA-aware cell library generator for FinFET structure with implicitly adjustable grid map」主題。共同形成了獨特的指紋。

引用此