NBL Causing Low Latch-up Immunity between HV-PMOS and LV-P/NMOS in a 0.15-μm BCD Process

Chao Yang Chen, Jian Hsing Lee, Karuna Nidhi, Tzer Yaa Bin, Geeng Lih Lin, Ming-Dou Ker

研究成果: Conference contribution同行評審

4 引文 斯高帕斯(Scopus)

摘要

The N-buried layer (NBL) causing low latch-up immunity between the HV-PMOS and LV-PMOS / LV-NMOS is studied in this work. The NBL layer has been often used to isolate the circuits from the common p-substrate for operating at different voltages, or to avoid noise coupling through the common p-substrate. As the HV circuits and LV circuits integrated together on the same silicon chip, the parasitic latchup paths between them would be easily triggered into a latch-up state under the current-trigger latch-up test. The latch-up or latch-up-like issues between the neighbor circuits with different power domains surrounding by NBL must be paid attention.

原文English
主出版物標題Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2021, EOS/ESD 2021
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)158537329X, 9781585373291
DOIs
出版狀態Published - 26 9月 2021
事件43rd Annual Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD 2021 - Tucson, 美國
持續時間: 26 9月 20211 10月 2021

出版系列

名字Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2021, EOS/ESD 2021

Conference

Conference43rd Annual Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD 2021
國家/地區美國
城市Tucson
期間26/09/211/10/21

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