Native-NMOS-triggered SCR (NANSCR) for ESD protection in 0.13-μm CMOS integrated circuits

Ming-Dou Ker; Kuo Chun Hsu

doi:10.1109/RELPHY.2004.1315356

Native-NMOS-triggered SCR (NANSCR) for ESD protection in 0.13-μm CMOS integrated circuits

Ming-Dou Ker^*, Kuo Chun Hsu

^*此作品的通信作者

研究成果: Conference article › 同行評審

10 引文斯高帕斯（Scopus）

摘要

A novel native-NMOS-triggered SCR (NANSCR) is proposed for efficient ESD protection design in a 0.13-μm CMOS process. As compared with the traditional LVTSCR, the trigger voltage, turn-on resistance, turn-on speed, and COM ESD level of NANSCR have been greatly improved to protect the ultra-thin gate oxide against ESD stresses. The proposed NANSCR can be designed for the input, output, and power-rail ESD protection circuits without latchup danger in a 0.13-μm CMOS process with VDD of 1.2 V. A new whole-chip ESD protection scheme realized with the NANSCR devices has been also demonstrated with the consideration of pin-to-pin ESD zapping.

原文	English
文章編號	1315356
頁（從 - 到）	381-386
頁數	6
期刊	IEEE International Reliability Physics Symposium Proceedings
卷	2004-January
發行號	January
DOIs	https://doi.org/10.1109/RELPHY.2004.1315356
出版狀態	Published - 4月 2004
事件	2004 IEEE International Reliability Physics Symposium Proceedings, 42nd Annual - Phoenix, AZ., United States 持續時間: 25 4月 2004 → 29 4月 2004

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10.1109/RELPHY.2004.1315356

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Link to publication in Scopus

引用此

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title = "Native-NMOS-triggered SCR (NANSCR) for ESD protection in 0.13-μm CMOS integrated circuits",

abstract = "A novel native-NMOS-triggered SCR (NANSCR) is proposed for efficient ESD protection design in a 0.13-μm CMOS process. As compared with the traditional LVTSCR, the trigger voltage, turn-on resistance, turn-on speed, and COM ESD level of NANSCR have been greatly improved to protect the ultra-thin gate oxide against ESD stresses. The proposed NANSCR can be designed for the input, output, and power-rail ESD protection circuits without latchup danger in a 0.13-μm CMOS process with VDD of 1.2 V. A new whole-chip ESD protection scheme realized with the NANSCR devices has been also demonstrated with the consideration of pin-to-pin ESD zapping.",

keywords = "CDM, ESD, ESD protection circuit, HBM, Latchup, SCR",

author = "Ming-Dou Ker and Hsu, {Kuo Chun}",

year = "2004",

month = apr,

doi = "10.1109/RELPHY.2004.1315356",

language = "English",

volume = "2004-January",

pages = "381--386",

journal = "IEEE International Reliability Physics Symposium Proceedings",

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note = "2004 IEEE International Reliability Physics Symposium Proceedings, 42nd Annual ; Conference date: 25-04-2004 Through 29-04-2004",

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AU - Ker, Ming-Dou

AU - Hsu, Kuo Chun

PY - 2004/4

Y1 - 2004/4

N2 - A novel native-NMOS-triggered SCR (NANSCR) is proposed for efficient ESD protection design in a 0.13-μm CMOS process. As compared with the traditional LVTSCR, the trigger voltage, turn-on resistance, turn-on speed, and COM ESD level of NANSCR have been greatly improved to protect the ultra-thin gate oxide against ESD stresses. The proposed NANSCR can be designed for the input, output, and power-rail ESD protection circuits without latchup danger in a 0.13-μm CMOS process with VDD of 1.2 V. A new whole-chip ESD protection scheme realized with the NANSCR devices has been also demonstrated with the consideration of pin-to-pin ESD zapping.

AB - A novel native-NMOS-triggered SCR (NANSCR) is proposed for efficient ESD protection design in a 0.13-μm CMOS process. As compared with the traditional LVTSCR, the trigger voltage, turn-on resistance, turn-on speed, and COM ESD level of NANSCR have been greatly improved to protect the ultra-thin gate oxide against ESD stresses. The proposed NANSCR can be designed for the input, output, and power-rail ESD protection circuits without latchup danger in a 0.13-μm CMOS process with VDD of 1.2 V. A new whole-chip ESD protection scheme realized with the NANSCR devices has been also demonstrated with the consideration of pin-to-pin ESD zapping.

KW - CDM

KW - ESD

KW - ESD protection circuit

KW - HBM

KW - Latchup

KW - SCR

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DO - 10.1109/RELPHY.2004.1315356

M3 - Conference article

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SN - 1541-7026

VL - 2004-January

SP - 381

EP - 386

JO - IEEE International Reliability Physics Symposium Proceedings

JF - IEEE International Reliability Physics Symposium Proceedings

IS - January

M1 - 1315356

T2 - 2004 IEEE International Reliability Physics Symposium Proceedings, 42nd Annual

Y2 - 25 April 2004 through 29 April 2004

ER -

Native-NMOS-triggered SCR (NANSCR) for ESD protection in 0.13-μm CMOS integrated circuits

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