Nanosized-Metal-Grain-Pattern-Dependent Threshold-Voltage Models for the Vertically Stacked Multichannel Gate-All-Around Si Nanosheet MOSFETs and Their Applications in Circuit Simulation

This article proposes grain-pattern-dependent threshold-voltage (<italic>V</italic> <inline-formula> <tex-math notation="LaTeX">$_{\text{th}}$</tex-math> </inline-formula>) models to predict the variability of <italic>V</italic> <inline-formula> <tex-math notation="LaTeX">$_{\text{th}}$</tex-math> </inline-formula> (<italic>V</italic> <inline-formula> <tex-math notation="LaTeX">$_{\text{th}}$</tex-math> </inline-formula>) due to work-function (WK) fluctuation (WKF) for the vertically stacked multichannel gate-all-around (GAA) silicon (Si) nanosheet (NS) MOSFETs (NS-FETs). In addition, the models were applied to estimate the variability of static noise margin (SNM) of a 6-T SRAM, a CMOS inverter, and a single-stage common-source amplifier. To model this phenomenon, each perturbed local metal grain is counted by the superposition principle statistically. The model can be used to explain the values of <italic>V</italic> <inline-formula> <tex-math notation="LaTeX">$_{\text{th}}$</tex-math> </inline-formula> by the location effect of metal grain for the vertically stacked multichannel devices. In addition, the model can predict the values of <italic>V</italic> <inline-formula> <tex-math notation="LaTeX">$_{\text{th}}$</tex-math> </inline-formula> for the vertically stacked multichannel devices with different metal grain sizes. Compared with the results of 3-D device simulation (3D-DS), the error rate (ER) of our model prediction is less than 0.5%. According to the formulated model, an empirical expression is further advanced, which has continuous derivatives and can be easily incorporated into a circuit simulator to assess the variability of SNM of a 6-T SRAM, CMOS inverter, and single-stage common-source amplifier affected by the WKF, where the ERs are below 0.5%. The proposed models provide a valuable approach for estimating the impact of circuit design by the WKF.