Nanoscaled interfacial oxide layers of bonded n - And p -type GaAs wafers

This work examined in detail the electrical characteristics and microstructures of in- and antiphase bonded interfaces for both n - and p -type GaAs wafers treated at 500 and 600 °C, respectively. The n-GaAs wafers did not bond directly to itself but instead via an amorphous oxide layer at 500 °C. These temperatures are lower than most other works. The nonlinear behavior of the current versus the voltage is related to the potential barrier formed at the continuous oxide interface. Both experimental observation and first-principles calculations confirm the existence of this barrier. The higher interface energy for the antiphase bonding tends to stabilize the interfacial oxide layer. The evolution of interfacial layers occurred much faster for the p -type wafers than for n -type wafers. Electrical performance was found to be closely related to the variation of nanosized interface morphology.