Nanoscale Transistors

Y. Li*, C. H. Hwang


研究成果: Chapter同行評審


Gate-length scaling is still the most effective way to apply Moore's law for transistor density increase and chip performance enhancement. Accompanied with complementary metal-oxide-semiconductor technology advanced to 45-nm node in production, further scaling down to sub-20. nm and even beyond has widely encountered many more challenges with short-channel control than previous generations. The worsened short-channel control of nanoscale transistor not only increases standby power dissipation, but also enlarges electrical characteristic fluctuations, such as the deviation of threshold voltage, drive current, mismatch, etc. The fluctuation budget has to be controlled ever tighter due to doubly increased transistor numbers along the technology node advancement. Moreover, the fluctuation is intrinsically increased with the scaling of transistor feature sizes, even when not considering worsened short-channel control. This chapter describes the structural evolution of the nanoscale transistor from planar transistor to double-gate, triple-gate, omega fin-type field effect transistors (FinFETs), and nanowire FinFETs. Another necessary consideration of transistor scaling, the intrinsic parameter fluctuations, is then examined in diverse nanoscale transistors and circuits. Reduction of the characteristic fluctuation by device and circuit design viewpoints is also discussed. Full realization of the benefit of nanoscale transistors therefore requires development and optimization of new device materials, structures, and technologies to maintain transistor performance and reliability.

主出版物標題Comprehensive Nanoscience and Technology
發行者Elsevier Inc.
出版狀態Published - 2011


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