Nanoscale p-MOS thin-film transistor with TiN gate electrode fabricated by low-temperature microwave dopant activation

Yu Lun Lu*, Fu Kuo Hsueh, Kuo Ching Huang, Tz Yen Cheng, Jeff M. Kowalski, Jeff E. Kowalski, Yao Jen Lee, Tien-Sheng Chao, Ching Yi Wu

*此作品的通信作者

研究成果: Article同行評審

15 引文 斯高帕斯(Scopus)

摘要

In this letter, nanoscale p-MOS TFTs with a TiN gate electrode were realized using a novel microwave (MW) dopant-activation technique. We compared both low-temperature MW annealing and rapid thermal annealing. We successfully activated the source/drain region and suppressed the short-channel effects using low-temperature MW annealing. This technique is promising from the viewpoint of realizing high-performance and low-cost upper layer nanoscale transistors required for low-temperature 3-D integrated circuit fabrication.

原文English
文章編號5427093
頁(從 - 到)437-439
頁數3
期刊IEEE Electron Device Letters
31
發行號5
DOIs
出版狀態Published - 1 5月 2010

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