@inproceedings{3238f51bd49b486aa7f8fd6e795193e0,
title = "Nano-scaled Ge FinFETs with low temperature ferroelectric HfZrO x on specific interfacial layers exhibiting 65% S.S. reduction and improved I ON",
abstract = " Ge n- and p-FinFETs with different interfacial layer ferroelectric HfZrO x (IL-FE-HZO) gate stacks have been demonstrated systematically by various annealing conditions for the first time. Microwave annealing (MWA) not only shows enhanced FE characteristics but also suppresses the gate leakage and Ge interdiffusion compared with conventional rapid thermal annealing (RTA). While HZO on Al 2 O 3 IL results in paraelectric behavior, HZO on GeO x IL exhibits significant FE. High I on /I off (> 107) and low subthreshold slope (S.S. ∼ 58 mV/dec.) are demonstrated by a Ge nFinFET with a gate length (L g ) of 60 nm and a FE-HZO/GeO x gate stack. ",
author = "Su, {C. J.} and Tang, {Y. T.} and Tsou, {Y. C.} and Sung, {P. J.} and Hou, {F. J.} and Wang, {C. J.} and Chung, {S. T.} and Hsieh, {C. Y.} and Yeh, {Y. S.} and Hsueh, {F. K.} and Kao, {K. H.} and Chuang, {S. S.} and Wu, {C. T.} and You, {T. Y.} and Jian, {Y. L.} and Chou, {T. H.} and Shen, {Y. L.} and Chen, {B. Y.} and Luo, {G. L.} and Hong, {T. C.} and Huang, {K. P.} and Chen, {M. C.} and Lee, {Y. J.} and Tien-Sheng Chao and Tseung-Yuen Tseng and Wu, {W. F.} and Huang, {G. W.} and Shieh, {J. M.} and Yeh, {W. K.} and Wang, {Y. H.}",
year = "2017",
month = jul,
day = "31",
doi = "10.23919/VLSIT.2017.7998159",
language = "English",
series = "Digest of Technical Papers - Symposium on VLSI Technology",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "T152--T153",
booktitle = "2017 Symposium on VLSI Technology, VLSI Technology 2017",
address = "United States",
note = "null ; Conference date: 05-06-2017 Through 08-06-2017",
}