@inproceedings{4baa6b3a35dc42cb9516e91bfdcadc98,
title = "Nano-meter scaled gate area high-K dielectrics with trap-assisted tunneling and random telegraph noise",
abstract = "If the trap density is 1012 cm-2, then there are only one trap in 10nm × 10nm on average. Accordingly, three-dimensional simulation that is sensitive to the movement of sole electron is indispensable for carefully investigating the reliability issues related to local traps in future nano-electron devices. As a demonstration, we investigate Random Telegraph Noise (RTN) and Trap-Assisted Tunneling (TAT) at the same moment in 5nm×5nm gate area high-K dielectrics (EOT= 0.8nm to 0.47nm). The simulation is carried out with respect to various gate biases, physical thickness of high-K, interlayer suboxide thickness, and dielectric constant of high-K. It is suggested that thinner suboxide and higher permittivity can suppress the increase of the leakage current which is caused by TAT.",
keywords = "high-K dielectrics, interlayer suboxide, random telegraph noise, simulation, single-electron, trap-assisted tunneling",
author = "Lin, {Po Jui Jerry} and Lee, {Zhe An Andy} and Yao, {Chih Wei Kira} and Lin, {Hsin Jyun Vincent} and Hiroshi Watanabe",
year = "2014",
month = oct,
day = "20",
doi = "10.1109/SISPAD.2014.6931608",
language = "English",
series = "International Conference on Simulation of Semiconductor Processes and Devices, SISPAD",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "241--244",
booktitle = "International Conference on Simulation of Semiconductor Processes and Devices, SISPAD",
address = "美國",
note = "2014 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2014 ; Conference date: 09-09-2014 Through 11-09-2014",
}