Nano-meter scaled gate area high-K dielectrics with trap-assisted tunneling and random telegraph noise

Po Jui Jerry Lin*, Zhe An Andy Lee, Chih Wei Kira Yao, Hsin Jyun Vincent Lin, Hiroshi Watanabe

*此作品的通信作者

研究成果: Conference contribution同行評審

摘要

If the trap density is 1012 cm-2, then there are only one trap in 10nm × 10nm on average. Accordingly, three-dimensional simulation that is sensitive to the movement of sole electron is indispensable for carefully investigating the reliability issues related to local traps in future nano-electron devices. As a demonstration, we investigate Random Telegraph Noise (RTN) and Trap-Assisted Tunneling (TAT) at the same moment in 5nm×5nm gate area high-K dielectrics (EOT= 0.8nm to 0.47nm). The simulation is carried out with respect to various gate biases, physical thickness of high-K, interlayer suboxide thickness, and dielectric constant of high-K. It is suggested that thinner suboxide and higher permittivity can suppress the increase of the leakage current which is caused by TAT.

原文English
主出版物標題International Conference on Simulation of Semiconductor Processes and Devices, SISPAD
發行者Institute of Electrical and Electronics Engineers Inc.
頁面241-244
頁數4
ISBN(電子)9781479952885
DOIs
出版狀態Published - 20 10月 2014
事件2014 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2014 - Yokohama, 日本
持續時間: 9 9月 201411 9月 2014

出版系列

名字International Conference on Simulation of Semiconductor Processes and Devices, SISPAD

Conference

Conference2014 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2014
國家/地區日本
城市Yokohama
期間9/09/1411/09/14

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