Multiplierless multirate decimator / interpolator module generator

Shyh-Jye Jou*, Kai Yuan Jheng, Hsiao Yun Chen, An Yeu Wu

*此作品的通信作者

    研究成果: Conference contribution同行評審

    7 引文 斯高帕斯(Scopus)

    摘要

    A module generator, which can automate the process of designing high-speed low-complexity multistage multirate decimator / interpolator, is presented. The generator exploit architectural symmetries in linear phase filters and multistage multirate interpolated FIR filter design methodology for low complexity. In addition, the polyphase representation is used to decompose the filter into subfilters. The resulting filters utilize canonic signed digit (CSD) multipliers, a transposed direct form structure, and carry-save addition for high speed. A filter design example with TSMC 0.25μm standard cell for 64-QAM baseband demodulator shows that the area is reduced by 39% for low-complexity applications. Moreover, for high-speed application, the chip can operate at 714MHz. Finally, a designed decimator which is used in the CDMA cellular shows that the area is reduced by 70% as compared with conventional approach.

    原文English
    主出版物標題Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits
    頁面58-61
    頁數4
    DOIs
    出版狀態Published - 1 12月 2004
    事件Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits - Fukuoka, Japan
    持續時間: 4 8月 20045 8月 2004

    出版系列

    名字Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits

    Conference

    ConferenceProceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits
    國家/地區Japan
    城市Fukuoka
    期間4/08/045/08/04

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