Multiplierless FIR filter architecture synthesizer based on CSD code

An architecture synthesizer for a FIR filter based on CSD code is presented. A traditional filter synthesis tool only generates one set of CSD coefficients that fits the filter specifications; however, using the time domain and then the frequency domain optimization of the filter coefficients, our synthesizer can obtain as many sets of CSD coefficients as possible. The coefficient set that leads to minimum hardware complexity will be selected. Then, the user can select four structures with different operational speed and hardware complexity. Finally, a synthesizable Verilog code will automatically be generated. A design example of a FIR filter that has 35 taps with 8-bit coefficients shows that the overall hardware reduction in using our synthesizer is 58% as compared to the result after the time domain optimization.