Multiplier architecture power consumption characterization for low-power DSP applications

Sangjin Hong*, Shu Shin Chin, Suhwan Kim, Wei Hwang

*此作品的通信作者

研究成果: Conference contribution同行評審

2 引文 斯高帕斯(Scopus)

摘要

This paper presents a multiplier power consumption characterization technique used in a coefficient optimization for low-power multimedia digital signal processing. The technique accurately characterizes and models the actual power consumption of the multipliers. Based on the models, the coefficient optimization finds an optimum set of coefficient patterns. The technique is based on the relative power weight factor of each coefficient bit is defined which characterizes the power consumption of multipliers. We have developed power consumption models based on the relative power weight factors to estimate/predict power dissipation for array-type multipliers and tree-type multipliers. We have applied our methodology on FFT for obtaining the profiles of power consumption for these multiplier structures.

原文English
主出版物標題ICECS 2002 - 9th IEEE International Conference on Electronics, Circuits and Systems
頁面741-744
頁數4
DOIs
出版狀態Published - 1 十二月 2002
事件9th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2002 - Dubrovnik, Croatia
持續時間: 15 九月 200218 九月 2002

出版系列

名字Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems
2

Conference

Conference9th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2002
國家/地區Croatia
城市Dubrovnik
期間15/09/0218/09/02

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