Multiple-patterning lithography-aware routing for standard cell layout synthesis

As features in semiconductor technology become extremely scaled down, manufacturability is becoming a great challenge. Owing to the delayed adoption of new lithographic techniques, such as extreme ultraviolet (EUV), e-beam direct-write (EBDW), and directed self-assembly (DSA), in IC volume production, double patterning lithography (DPL) or multiple patterning lithography (MPL) is used to print critical features in advanced technology nodes. DPL/MPL imposes many restrictive design rules on the mask layout and most of previous works discuss their impact on the design of interconnection, especially on block and chip level routing. The layout decomposition problem and multiple-patterning lithography aware routing problem have been widely studied in relation to DPL/MPL for resolving the manufacturing problem at the stages of post-routing and routing respectively. The same challenges also happen in standard cell layout synthesis problem that has another limited area constraint and transistor design rules to lower the feasibility of synthesis algorithms. This paper provides an overview of issues in DPL/MPL and focus on the gridless routing model, which is suitable for accommodating the restrictive design rules that are imposed by DPL/MPL. The routability problem of the standard cell layout synthesis under conditional design rules in advanced nodes will also be addressed.