A multichip module (MCM) based RISC processor with programmable hardware has been developed for the new era of miniaturized spacecraft required for NASA's 'faster, better, cheaper' missions. The MCM based processor incorporates a complete 32-bit RISC computer including RAM, EEPROM and programmable hardware. This paper describes the system architecture and its associated MCM design and implementation. It also explores the architectural merits of including user programmable hardware.
|頁（從 - 到）||119-122|
|期刊||Proceedings of the Annual IEEE International ASIC Conference and Exhibit|
|出版狀態||Published - 1 12月 1995|
|事件||Proceedings of the 8th Annual IEEE International ASIC Conference and Exhibit - Austin, TX, USA|
持續時間: 18 9月 1995 → 22 9月 1995