Multi-step incremental ADC with extended binary counting

Y. Zhang; Chia-Hung Chen; T. He; G. C. Temes

doi:10.1049/el.2016.0151

Multi-step incremental ADC with extended binary counting

Y. Zhang^*, Chia-Hung Chen, T. He, G. C. Temes

^*此作品的通信作者

電機工程學系

研究成果: Article › 同行評審

8 引文斯高帕斯（Scopus）

摘要

A multi-step incremental ADC (IADC) with extended binary counting is proposed. It achieves high accuracy by splitting one conversion cycle into two serial steps. During the first step, the ADC works as a first-order IADC (IADC1). The second step reuses the single integrator and extends the accuracy to 18 bits by a binary counting technique. For the same accuracy, the conversion cycle is shortened by a factor of more than 28 as compared with the single-step IADC.

原文	English
頁（從 - 到）	697-699
頁數	3
期刊	Electronics Letters
卷	52
發行號	9
DOIs	https://doi.org/10.1049/el.2016.0151
出版狀態	Published - 28 4月 2016

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10.1049/el.2016.0151

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abstract = "A multi-step incremental ADC (IADC) with extended binary counting is proposed. It achieves high accuracy by splitting one conversion cycle into two serial steps. During the first step, the ADC works as a first-order IADC (IADC1). The second step reuses the single integrator and extends the accuracy to 18 bits by a binary counting technique. For the same accuracy, the conversion cycle is shortened by a factor of more than 28 as compared with the single-step IADC.",

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AU - Temes, G. C.

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AB - A multi-step incremental ADC (IADC) with extended binary counting is proposed. It achieves high accuracy by splitting one conversion cycle into two serial steps. During the first step, the ADC works as a first-order IADC (IADC1). The second step reuses the single integrator and extends the accuracy to 18 bits by a binary counting technique. For the same accuracy, the conversion cycle is shortened by a factor of more than 28 as compared with the single-step IADC.

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Multi-step incremental ADC with extended binary counting

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