Multi-sensory combined integrated low power tunable-gain interface circuit

Chun Te Tung, Kuei-Ann Wen

    研究成果: Conference contribution同行評審

    摘要

    This paper presents MEMS multi-sensors with low power tunable-gain interface circuit that can be monolithically integrated in the ASIC compatible standard CMOS process. A high gain ultra-low power sustaining TIA amplifier circuit with PLL compactly has been integrated with the resonator-based core sensing structure. The proposed low-power readout circuit adopts Correlated Double Sampling (CDS) to suppress low frequency noise and compensate DC offset. The gyroscope sensitivity is designed to be 1.8 aF/°/sec within ±100 °/sec. The tunable sensitivity can be adjusted from 28 mV/fF to 224 mV/fF by fully-differential programmable-gain amplifier (PGA). The interface circuit has 61.12dB SNR under 500 KHz sampling rate.

    原文English
    主出版物標題China Semiconductor Technology International Conference 2017, CSTIC 2017
    編輯Steve Liang, Ying Shi, Ru Huang, Qinghuang Lin, David Huang, Hanming Wu, Yuchun Wang, Cor Claeys, Kafai Lai, Ying Zhang, Peilin Song, Viyu Shi, Zhen Guo
    發行者Institute of Electrical and Electronics Engineers Inc.
    ISBN(電子)9781509066940
    DOIs
    出版狀態Published - 4 5月 2017
    事件2017 China Semiconductor Technology International Conference, CSTIC 2017 - Shanghai, China
    持續時間: 12 3月 201713 3月 2017

    出版系列

    名字China Semiconductor Technology International Conference 2017, CSTIC 2017

    Conference

    Conference2017 China Semiconductor Technology International Conference, CSTIC 2017
    國家/地區China
    城市Shanghai
    期間12/03/1713/03/17

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