Multi-level parallelism analysis of face detection on a shared memory multi-core system

Chih Hsuan Chiang*, Chih Heng Kao, Guan Ru Li, Bo-Cheng Lai

*此作品的通信作者

    研究成果: Conference contribution同行評審

    10 引文 斯高帕斯(Scopus)

    摘要

    Face detection is one of the fundamental technologies for the future smart objects. However, its computation intensive property thwarts the practice of a real-time application on an embedded device. Parallel processing and many-core architecture have become a mainstream to achieve high performance in the future computing systems. The parallelism of an application needs to be exposed before being exploited by the parallel architecture. This paper performs a comprehensive analysis of the parallelism of a face detection algorithm at different algorithmic levels. This paper has demonstrated that each parallelism level has its own potential to enhance performance, but also imposes different limiting factors to the overall performance. Based on the analysis results and design experience, this paper proposes a multi-staged mixed-level parallelization scheme to retain the performance scalability and avoid the limiting factors. With this scheme, we are able to achieve up to 37.5x performance enhancement on a 64-core system.

    原文English
    主出版物標題Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011
    頁面328-331
    頁數4
    DOIs
    出版狀態Published - 28 6月 2011
    事件2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011 - Hsinchu, Taiwan
    持續時間: 25 4月 201128 4月 2011

    出版系列

    名字Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011

    Conference

    Conference2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011
    國家/地區Taiwan
    城市Hsinchu
    期間25/04/1128/04/11

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