Multi-gigabit serial link transmitter- Off-chip and on-chip

Shyh-Jye Jou*, Chih Hsien Lin, Chih Ning Chen, You Jiun Wang, Ju Yuan Hsiao

*此作品的通信作者

    研究成果: Conference contribution同行評審

    摘要

    Multi-Gbps serial link transmitter for both off-chip and on-chip transmission are presented. For off-chip transmission, a new pre-emphasis design methodology and circuits for a 4/2 PAM transmitter over cable are proposed. A test chip of transmitter with pre-emphasis, PLL circuit and on-chip termination resistors is implemented using tsmc 0.18 um CMOS process. The measurement results of 10/5 Gbps (4/2 PAM) are carried out over 5 meter (m) long cable and is in agreement with our analysis and simulation results. For on-chip transmission, SerDes based serial link architecture is used in on-chip application. Using tsmc 0.13 um CMOS process, the operation speed and power consumption are 5 Gbps and 3.2 mW respectively with the interconnect area is half of parallel architecture.

    原文English
    主出版物標題Emerging Information Technology Conference 2005
    頁面137-140
    頁數4
    DOIs
    出版狀態Published - 2005
    事件Emerging Information Technology Conference 2005 - Taipei, Taiwan
    持續時間: 15 8月 200516 8月 2005

    出版系列

    名字Emerging Information Technology Conference 2005
    2005

    Conference

    ConferenceEmerging Information Technology Conference 2005
    國家/地區Taiwan
    城市Taipei
    期間15/08/0516/08/05

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