## 摘要

MOTA; a new NMOS and CMOS timing simulator, is presented. Basically, it employs a one sweep nonlinear Gauss-Seidal relaxation technique to decouple node equations, and this results in a linear performance on the computation time over the number of the gates of the circuit. It has three features: (a) it provides a 'SUBCIRCUIT' capability to simulate tightly-coupled circuit blocks. This solves the inaccuracy and the instability problems which are usually encountered in existing timing simulators, (b) it employs a physical table model for MOS devices with only 250 storage points, and (c) it utilizes a simple variable time step control scheme and internal and external bypass schemes to increase the simulation speed. Examples show that it is approximately 60 times faster than SPICE2G-5 while giving comparable precision.

原文 | English |
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頁（從 - 到） | 193-199 |

頁數 | 7 |

期刊 | IEE Proceedings I: Solid State and Electron Devices |

卷 | 133 |

發行號 | 5 |

DOIs | |

出版狀態 | Published - 1 1月 1986 |