MOS-bounded diodes for on-chip ESD protection in a 0.15-μm shallow-trench-isolation salicided CMOS process

Ming-Dou Ker, Kun Hsien Lin, Che Hao Chuang

    研究成果: Conference contribution同行評審

    2 引文 斯高帕斯(Scopus)

    摘要

    Novel diode structures without the shallow trench isolation (STI) across the p/n junction for ESD protection in a 0.15-um CMOS process are proposed. A NMOS (PMOS) is especially inserted into the diode structure to form the NMOS-bounded (PMOS-bounded) diode, which is used to block the STI isolation across the p/n junction in the diode structure. Without the STI boundary across the p/n junction of diode structure, the proposed PMOS-bounded and NMOS-bounded diodes can provide more effective protection to the internal circuits, as compared to the other diode structures under reversebiased condition. Such PMOS-bounded and NMOS-bounded dodes are fully process-compatible to general CMOS processes without additional process modification or mask layers.

    原文English
    主出版物標題VLSI 2003 - 2003 20th International Symposium on VLSI Technology, Systems and Applications, Proceedings
    發行者Institute of Electrical and Electronics Engineers Inc.
    頁面84-87
    頁數4
    ISBN(電子)0780377656
    DOIs
    出版狀態Published - 1 1月 2003
    事件20th International Symposium on VLSI Technology, Systems and Applications, VLSI 2003 - Hsinchu, Taiwan
    持續時間: 6 10月 20038 10月 2003

    出版系列

    名字International Symposium on VLSI Technology, Systems, and Applications, Proceedings
    2003-January
    ISSN(列印)1930-8868

    Conference

    Conference20th International Symposium on VLSI Technology, Systems and Applications, VLSI 2003
    國家/地區Taiwan
    城市Hsinchu
    期間6/10/038/10/03

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